module lvds_top (
    input 					inclk,
    input						pll_rst,
    output	[1:0]			tx_rdy,        //
    input						tx_nce,
    input						tx_nwe,
    input		[8:0]			tx_rd_addr_ab,
    input		[8:0]			tx_data,
    output	[8:0] tx_rd_data,
    output 				tx,
    input						rx,
    input						rx_nce,
    input						rx_noe,
    input						rx_nwe,
    output [8:0] rx_data,
    output					rx_rdy,
    output	[8:0]			rx_addr,       //
    output					clk_10M,
    output pll_locked
  );

  wire clk_100M,clk_400M;
  wire   rst = !pll_locked;

  trans_data_buf   trans_data_buf_inst  //transmit data
                   (
                     .rst				(rst),
                     .clk_10M			(clk_10M),
                     .clk_100M		(clk_100M),
                     .tx_nce			(tx_nce),
                     .tx_nwe			(tx_nwe),

                     .tx_rdy			(tx_rdy),
                     .tx_addr			(tx_rd_addr_ab),
                     .tx_data			(tx_data),
                     .tx_rd_data		(tx_rd_data),
                     .tx_out			(tx)
                   );

  recv_data_buf
    #(
      .SYNC1(10'b1010_1010_10),
      .SYNC2(10'b1010_1010_11)
    )
    recv_data_buf_inst
    (
      .rst						(rst),
      .clk_100M				(clk_100M),
      .clk_400M				(clk_400M),

      .rx						(rx),
      .rx_nce					(rx_nce),
      .rx_noe					(rx_noe),
      .rx_nwe					(rx_nwe),
      .rx_rdy					(rx_rdy),
      .rx_addr					(rx_addr),
      .rx_data					(rx_data)
    );

  plltx_rx	plltx_rx_inst (
             .areset (pll_rst),
             .inclk0 (inclk),
             .c0 (clk_10M),
             .c1 (clk_100M),
             .c2 (clk_400M),
             .locked (pll_locked)
           );

endmodule
